EP2SGX30C Datasheet, PDF (271/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Table 4–89. Stratix II GX Maximum Input Clock Rate for Row I/O Pins (Part 2 of 2)
I/O Standard
Differential SSTL-2
Class II
Differential SSTL-18
Class I
Differential SSTL-18
Class I I
1.8-V differential
HSTL Class I
1.8-V differential
HSTL Class I I
1.5-V differential
HSTL Class I
1.5-V differential
HSTL Class II
LVDS (1)
HyperTransport
-3 Speed Grade
500
500
500
500
500
500
500
520
520
-4 Speed Grade
500
500
500
500
500
500
500
520
520
-5 Speed Grade
500
500
500
500
500
500
500
420
420
Note to Table 4–89:
(1) The parameters are only available on the left side of the device.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–90 shows the maximum input clock toggle rates for Stratix II GX
device dedicated clock pins.
Table 4–90. Stratix II GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2)
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL CLass I
-3 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
-5 Speed Grade
400
400
400
400
400
500
500
500
500
500
500
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
October 2007
4–101
Stratix II GX Device Handbook, Volume 1