EP2SGX30C Datasheet, PDF (300/314 Pages) Altera Corporation – Stratix II GX Device

PLL Timing Specifications
PLL Timing
Specifications
Tables 4–110 and 4–111 describe the Stratix II GX PLL specifications when
operating in both the commercial junction temperature range (0 to 85 C)
and the industrial junction temperature range (–40 to 100 C), except for
the clock switchover and phase-shift stepping features. These two
features are only supported from the 0 to 100 C junction temperature
range.
Table 4–110. Enhanced PLL Specifications (Part 1 of 2)
Name
f_IN
f_INPFD
f_INDUTY
f_ENDUTY
t_INJITTER
t_OUTJITTER
t_FCOMP
f_OUT
f_SCANCLK
t_CONFIGEPLL
f_{OUT_EXT}
t_LOCK
t_DLOCK
f_SWITCHOVER
f_CLBW
f_VCO
Description
Min
Typ
Input clock frequency
4
Input frequency to the PFD
4
Input clock duty cycle
40
External feedback input clock duty cycle
40
Input or external feedback clock input jitter
0.5
tolerance in terms of period jitter.
Bandwidth ≤0.85 MHz
Input or external feedback clock input jitter
1.0
tolerance in terms of period jitter.
Bandwidth > 0.85 MHz
Dedicated clock output period jitter
50
100
External feedback compensation time
Output frequency for internal global or
regional clock
Scanclk frequency
1.5 (2)
Time required to reconfigure scan chains
for EPLLs
PLL external clock output frequency
174/f_SCANCLK
1.5 (2)
Time required for the PLL to lock from the
0.03
time it is enabled or the end of device
configuration
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical clock
frequencies
Frequency range where the clock
switchover performs properly
1.5
1
PLL closed-loop bandwidth
0.13
1.2
PLL VCO operating range for –3 and –4
300
speed grade devices
PLL VCO operating range for –5 speed
300
grade devices
Max Unit
500 MHz
420 MHz
60
%
60
%
ns (peak-
to-peak)
ns (peak-
to-peak)
250 ps (p-p)
10
ns
550 MHz
100 MHz
ns
(1)
MHz
1
ms
1
ms
500 MHz
16.9
1,040
MHz
MHz
840 MHz
4–130
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007