EP2SGX30C Datasheet, PDF (105/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
The Stratix II GX clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state, thereby reducing the overall
power consumption of the device. The global and regional clock
networks can be powered down statically through a setting in the
configuration file (.sof or .pof). Clock networks that are not used are
automatically powered down through configuration bit settings in the
configuration file generated by the Quartus II software. The dynamic
clock enable and disable feature allows the internal logic to control power
up and down synchronously on GCLK and RCLK nets and PLL_OUT pins.
This function is independent of the PLL and is applied directly on the
clock network or PLL_OUT pin, as shown in Figures 2–67 through 2–69.
Enhanced and Fast PLLs
Stratix II GX devices provide robust clock management and synthesis
using up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
clocking, reconfigurable bandwidth, phase control, and reconfigurable
phase shifting, the Stratix II GX device’s enhanced PLLs provide you with
complete control of clocks and system timing. The fast PLLs provide
general purpose clocking with multiplication and phase shifting as well
as high-speed outputs for high-speed differential I/O support. Enhanced
and fast PLLs work together with the Stratix II GX high-speed I/O and
advanced clock architecture to provide significant improvements in
system performance and bandwidth.
Altera Corporation
October 2007
2–97
Stratix II GX Device Handbook, Volume 1