EP2SGX30C Datasheet, PDF (100/314 Pages) Altera Corporation – Stratix II GX Device

PLLs and Clock Networks
Figure 2–63. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[15..12]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
CLK[15..12]
CLK[3..0]
PLLs
CLK[7..4]
CLK[3..0]
PLLs
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and 8 regional clock lines. Multiplexers
are used with these clocks to form buses to drive LAB row clocks, column
IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB
level to select three of the six row clocks to feed the ALM registers in the
LAB (see Figure 2–64).
Figure 2–64. Hierarchical Clock Networks per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Global Clock Network [15..0]
Clock [23..0]
Regional Clock Network [7..0]
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
2–92
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007