XQ2V1000_1 Datasheet, PDF (79/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
FG456 Fine-Pitch BGA Package
The XQ2V1000 QPro Virtex-II device is available in the FG456 fine-pitch BGA package. Pins definitions listed in Table 72
are identical to the commercial grade XC2V1000-FG456. Following this table are the "FG456 Fine-Pitch BGA Package
Specifications (1.00 mm pitch)," page 85.
Table 72: FG456 BGA — XQ2V1000
Bank
Pin Description
0
IO_L01N_0
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0/VRP_0
0
IO_L03P_0/VRN_0
0
IO_L04N_0/VREF_0
0
IO_L04P_0
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L21N_0
0
IO_L21P_0/VREF_0
0
IO_L22N_0
0
IO_L22P_0
0
IO_L24N_0
0
IO_L24P_0
0
IO_L49N_0
0
IO_L49P_0
0
IO_L51N_0
0
IO_L51P_0/VREF_0
0
IO_L52N_0
0
IO_L52P_0
0
IO_L54N_0
0
IO_L54P_0
0
IO_L91N_0/VREF_0
0
IO_L91P_0
0
IO_L92N_0
0
IO_L92P_0
0
IO_L93N_0
0
IO_L93P_0
0
IO_L94N_0/VREF_0
0
IO_L94P_0
0
IO_L95N_0/GCLK7P
0
IO_L95P_0/GCLK6S
Pin Number
B4
A4
C4
C5
B5
A5
D6
C6
B6
A6
E7
E8
D7
C7
B7
A7
D8
C8
B8
A8
E9
F9
D9
C9
B9
A9
E10
F10
D10
C10
B10
A10
E11
F11
D11
C11
Table 72: FG456 BGA — XQ2V1000 (Cont’d)
Bank
Pin Description
Pin Number
0
IO_L96N_0/GCLK5P
B11
0
IO_L96P_0/GCLK4S
A11
1
IO_L96N_1/GCLK3P
F12
1
IO_L96P_1/GCLK2S
F13
1
IO_L95N_1/GCLK1P
E12
1
IO_L95P_1/GCLK0S
D12
1
IO_L94N_1
C12
1
IO_L94P_1/VREF_1
B12
1
IO_L93N_1
A13
1
IO_L93P_1
B13
1
IO_L92N_1
C13
1
IO_L92P_1
D13
1
IO_L91N_1
E13
1
IO_L91P_1/VREF_1
E14
1
IO_L54N_1
A14
1
IO_L54P_1
B14
1
IO_L52N_1
C14
1
IO_L52P_1
D14
1
IO_L51N_1/VREF_1
A15
1
IO_L51P_1
B15
1
IO_L49N_1
C15
1
IO_L49P_1
D15
1
IO_L24N_1
F14
1
IO_L24P_1
E15
1
IO_L22N_1
A16
1
IO_L22P_1
B16
1
IO_L21N_1/VREF_1
C16
1
IO_L21P_1
D16
1
IO_L06N_1
E16
1
IO_L06P_1
E17
1
IO_L05N_1
A17
1
IO_L05P_1
B17
1
IO_L04N_1
C17
1
IO_L04P_1/VREF_1
D17
1
IO_L03N_1/VRP_1
A18
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
79