XQ2V1000_1 Datasheet, PDF (2/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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• SRAM-based in-system configuration
♦ Fast SelectMAP configuration
♦ Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
♦ IEEE 1532 support
♦ Partial reconfiguration
QPro Virtex-II 1.5V Platform FPGAs
♦ Unlimited reprogrammability
♦ Readback capability
• 0.15 µm 8-layer metal process with 0.12 µm high-
speed transistors
• 1.5V (V_CCINT) core power supply, dedicated 3.3V
V_CCAUX auxiliary and V_CCO I/O power supplies
• IEEE 1149.1 compatible Boundary-Scan logic support
General Description
The Virtex-II family includes platform FPGAs developed for
high performance from low-density to high-density designs
that are based on IP cores and customized modules. The
family delivers complete solutions for telecommunication,
wireless, networking, video, and DSP applications,
including PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide
variety of flexible features and a large range of densities up
to 8 million system gates, the Virtex-II family enhances
programmable logic design capabilities and is a powerful
alternative to mask-programmed gates arrays. As shown in
Table 1, the QPro Virtex-II family comprises three members,
ranging from 1M to 6M system gates.
Table 1: Virtex-II Field-Programmable Gate Array Family Members
Device
System
Gates
CLB
(1 CLB = 4 slices = Max 128 bits)
Array
Row x Col.
Slices
Maximum
Distributed
RAM Kbits
Multiplier
Blocks
XQ2V1000
1M
40 x 32
5,120
160
40
XQ2V3000
3M
64 x 56
14,336
448
96
XQ2V6000
6M
96 x 88
33,792
1,056
144
SelectRAM Blocks
18 Kbit
Blocks
40
96
144
Max RAM
(Kbits)
720
1,728
2,592
DCMs
Max I/O
Pads⁽¹⁾
8
432
12
720
12
1,104
Notes:
1. See details in Table 2.
Packaging
Offerings include ball grid array (BGA) packages with
1.00 mm and 1.27 mm pitches. In addition to traditional
wire-bond interconnects, flip-chip interconnect is used in
some of the CGA offerings. The use of flip-chip interconnect
offers more I/Os than is possible in wire-bond versions of
the similar packages. Flip-chip construction offers the
combination of high pin count with high thermal capacity.
Table 2 shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table 5,
page 6) details the maximum number of I/Os for each
device and package using wire-bond or flip-chip technology.
Table 2: Maximum Number of User I/O Pads
Device
XQ2V1000
XQ2V3000
XQ2V6000
Wire-Bond
328
516
–
Flip-Chip
–
–
824
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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