XQ2V1000_1 Datasheet, PDF (27/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
3-State Buffers
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip buses. Each 3-state buffer has its
own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buffers
through the switch matrix, as shown in Figure 28. TBUFs in
neighboring CLBs can access slice outputs by direct
connects. The outputs of the 3-state buffers drive horizontal
routing resources used to implement 3-state buses.
X-Ref Target - Figure 28
TBUF
X-Ref Target - Figure 29
Switch
Matrix
TBUF
Slice
S1
Slice
S3
Slice
S2
Slice
S0
DS031_37_060700
Figure 28: Virtex-II 3-State Buffers
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predictable
and less load dependent especially with larger devices.
Locations/Organization
Four horizontal routing resources per CLB are provided for
on-chip 3-state buses. Each 3-state buffer has access
alternately to two horizontal lines, which can be partitioned as
shown in Figure 29. The switch matrices corresponding to
SelectRAM memory and multiplier or I/O blocks are skipped.
Number of 3-State Buffers
Table 15 shows the number of 3-state buffers available in
each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.
Table 15: Virtex-II 3-State Buffers
Device
3-State Buffers
per Row
XQ2V1000
64
XQ2V3000
112
XQ2V6000
176
Total Number
of 3-State Buffers
2,560
7,168
16,896
3 - state lines
Switch
matrix
CLB-II
Programmable
connection
Switch
matrix
CLB-II
DS031_09_032700
Figure 29: 3-State Buffer Connection to Horizontal Lines
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
27