XQ2V1000_1 Datasheet, PDF (28/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
CLB/Slice Configurations
Table 16 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed. Table 17 shows the available resources in all CLBs.
Table 16: Logic Resources in One CLB
Slices
LUTs
Flip-Flops MULT_ANDs
4
8
8
8
Arithmetic &
Carry Chains
2
SOP
Chains
2
Distributed
SelectRAM
128 bits
Shift
Registers
128 bits
TBUF
2
Table 17: Virtex-II Logic Resources Available in All CLBs
Device
CLB Array:
Row x
Column
Number
of Slices
Number
of
LUTs
Max Distributed
SelectRAM or Shift
Register (bits)
XQ2V1000
40 x 32
5,120
10,240
163,840
XQ2V3000
64 x 56
14,336 28,672
458,752
XQ2V6000
96 x 88
33,792 67,584
1,081,344
Notes:
1. The carry chains and SOP chains can be split or cascaded.
Number
of
Flip-Flops
10,240
28,672
67,584
Number
of
Carry Chains⁽¹⁾
64
112
176
Number of
SOP
Chains⁽¹⁾
80
128
192
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
28