XQ2V1000_1 Datasheet, PDF (55/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
IOB Input Switching Characteristics Standard Adjustments
Table 40: IOB Input Switching Characteristics Standard Adjustments
Description
Symbol
Standard
Data Input Delay Adjustments
Standard-specific data input delay adjustments
T_ILVTTL
T_ILVCMOS33
T_ILVCMOS25
T_ILVCMOS18
T_ILVCMOS15
T_{ILVDS_25}
T_{ILVDS_33}
T_{ILVPECL_33}
T_{IPCI33_3}
T_{IPCI66_3}
T_IPCIX
T_IGTL
T_IGTLP
T_{IHSTL_I}
T_{IHSTL_II}
T_{IHSTL_III}
T_{IHSTL_IV}
T_{IHSTL_I_18}
T_{IHSTL_II_18}
T_{IHSTL_III_18}
T_{IHSTL_IV_18}
T_{ISSTL2_I}
T_{ISSTL2_II}
T_{ISSTL3_I}
T_{ISSTL3_II}
T_IAGP
T_{ILVDCI_33}
T_{ILVDCI_25}
T_{ILVDCI_18}
T_{ILVDCI_15}
T_{ILVDCI_DV2_33}
T_{ILVDCI_DV2_25}
T_{ILVDCI_DV2_18}
T_{ILVDCI_DV2_15}
T_{IGTL_DCI}
T_{IGTLP_DCI}
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVDS_25
LVDS_33
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI–X, 133 MHz,
3.3V
GTL
GTLP
HSTL I
HSTL II
HSTL III
HSTL IV
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
AGP
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
Speed Grade
-5
-4
0.00
0.00
0.00
0.00
0.11
0.12
0.43
0.49
1.00
1.15
0.60
0.69
0.60
0.69
0.60
0.69
0.00
0.00
0.00
0.00
0.00
0.00
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.35
0.40
0.35
0.40
0.35
0.40
0.00
0.00
0.11
0.12
0.43
0.49
1.00
1.14
0.00
0.00
0.11
0.12
0.43
0.49
1.00
1.14
0.42
0.48
0.42
0.48
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
55