XQ2V1000_1 Datasheet, PDF (23/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

R
X-Ref Target - Figure 23
1 Shift Chain
in CLB
IN
DI
D
FF
SRLC16
MC15
SLICE S3
DI _D
FF
SRLC16
MC15
SHIFTOUT
SHIFTIN
DI _D
FF
SRLC16
MC15
SLICE S2
DI _D
FF
SRLC16
MC15
SHIFTOUT
SHIFTIN
DI _D
FF
SRLC16
MC15
DI _D
SRLC16
MC15
FF
SLICE S1
SHIFTOUT
SHIFTIN
DI _D
FF
SRLC16
MC15
DI _D
SRLC16
MC15
FF
SLICE S0
OUT
CASCADABLE OUT
CLB
DS031_06_110200
Figure 23: Cascadable Shift Register
QPro Virtex-II 1.5V Platform FPGAs
Multiplexers
Virtex-II function generators and associated multiplexers
can implement the following:
• 4:1 multiplexer in one slice
• 8:1 multiplexer in two slices
• 16:1 multiplexer in one CLB element (4 slices)
• 32:1 multiplexer in two CLB elements (8 slices)
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in Figure 24,
page 24. Each CLB element has two MUXF6 multiplexers,
one MUXF7 multiplexer and one MUXF8 multiplexer
(examples of multiplexers are shown in [Ref 1]). Any LUT
can implement a 2:1 multiplexer.
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the Figure 25, page 25.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedicated
carry path and carry multiplexer (MUXCY) can also be used
to cascade function generators for implementing wide logic
functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a 2-bit
full adder to be implemented within a slice. In addition, a
dedicated AND (MULT_AND) gate (shown in Figure 17,
page 20) improves the efficiency of multiplier implementation.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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