XQ2V1000_1 Datasheet, PDF (74/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for QPro Virtex-II source-
synchronous transmitter and receiver data-valid windows.
Table 65: Duty Cycle Distortion and Clock-Tree Skew
Description
Duty Cycle Distortion⁽¹⁾
Clock Tree Skew⁽²⁾
Symbol
T_{DCD_CLK0}
T_{DCD_CLK180}
T_CKSKEW
Device
All
All
XQ2V1000
XQ2V3000
XQ2V6000
Speed Grade
-5
-4
140
140
50
50
80
90
100
110
500
550
Units
ps
ps
ps
ps
ps
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
T_{DCD_CLK0} applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
T_{DCD_CLK180} applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element in the
I/O.
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists
for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing
Analyzer tools to evaluate clock skew specific to your application.
Table 66: Package Skew
Description
Package Skew⁽¹⁾
Symbol
T_PKGSKEW
Device/Package
XQ2V6000/CF1144
Value
90
Units
ps
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball
(7.1 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 67: Sample Window
Description
Sampling Error at Receiver Pins⁽¹⁾
Symbol
T_SAMP
Device
XQ2V1000
XQ2V3000
XQ2V6000
Speed Grade
-5
-4
500
550
500
550
500
550
Units
ps
ps
ps
Notes:
1. This parameter indicates the total sampling error of QPro Virtex-II DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include
♦ CLK0 and CLK180 DCM jitter
♦ Worst-case Duty-Cycle Distortion - T_{DCD_CLK180}
♦ DCM accuracy (phase offset)
♦ DCM phase shift resolution.
These measurements do not include package or clock tree skew.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
74