XQ2V1000_1 Datasheet, PDF (57/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments," page 58.
Table 41: IOB Output Switching Characteristics
Description
Propagation Delays
O input to Pad
O input to Pad via transparent latch
3-State Delays
T input to Pad high-impedance⁽¹⁾
T input to valid data on Pad
T input to Pad high-impedance via transparent latch⁽¹⁾
T input to valid data on Pad via transparent latch
GTS to Pad high-impedance⁽¹⁾
Sequential Delays
Clock CLK to Pad
Clock CLK to Pad high-impedance (synchronous)⁽¹⁾
Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times Before/After Clock CLK
O input
OCE input
SR input (OFF)
3–State Setup Times, T input
3–State Setup Times, TCE input
3–State Setup Times, SR input (TFF)
Set/Reset Delays
SR input to Pad (asynchronous)
SR input to Pad high-impedance (asynchronous)⁽¹⁾
SR input to valid data on Pad (asynchronous)
GSR to Pad
Notes:
1. The 3-state turn-off delays should not be adjusted.
Symbol
Speed Grade
-5
-4
Units
T_IOOP
T_IOOLP
1.51
1.74
ns
1.83
2.11
ns
T_IOTHZ
T_IOTON
T_IOTLPHZ
T_IOTLPON
T_GTS
0.56
0.64
ns
1.45
1.67
ns
0.88
1.01
ns
1.77
2.04
ns
5.20
5.98
ns
T_IOCKP
T_IOCKHZ
T_IOCKON
1.87
2.15
ns
1.04
1.20
ns
1.94
2.22
ns
T_IOOCK/T_IOCKO
0.34/–0.09 0.39/–0.11
ns
T_IOOCECK/T_IOCKOCE 0.21/–0.07 0.24/–0.08
ns
T_IOSRCKO/T_IOCKOSR 0.30/–0.06 0.34/–0.07
ns
T_IOTCK/T_IOCKT
0.31/–0.07 0.35/–0.08
ns
T_IOTCECK/T_IOCKTCE 0.21/–0.07 0.24/–0.08
ns
T_IOSRCKT/T_IOCKTSR 0.30/–0.06 0.34/–0.07
ns
T_IOSRP
T_IOSRHZ
T_IOSRON
T_IOGSRQ
2.59
2.98
ns
1.67
1.92
ns
2.56
2.95
ns
5.98
6.88
ns
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
57