XQ2V1000_1 Datasheet, PDF (20/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
The set and reset functionality of a register or a latch can be
configured as follows:
• No set or reset
• Synchronous set
• Synchronous reset
• Synchronous set and reset
X-Ref Target - Figure 17
SHIFTIN
• Asynchronous set (preset)
• Asynchronous reset (clear)
• Asynchronous set and reset (preset and clear)
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
COUT
SOPIN
G4
G3
G2
G1
WG4
WG3
WG2
WG1
ALTDIG
BY
SLICEWE[2:0]
ORCY
0
Dual-Port
Shift-Reg
A4
1
A3 ^LUT
A2
A1
WG4
RAM
ROM
D
WG3 ^G
WG2
WG1
MC15
WS DI
MUXCY
01
MULTAND
G2
PROD
G1
1 ^BY
0
CYOG
YBMUX
GYMUX
XORG
FF
LATCH
DYMUX
CE
CLK
D
Q
Y
CE
CK
SR REV
WSG
SHIFTOUT
SR
WE[2:0]
WE
CLK
WSF
MUXCY
0
1
SOPOUT
YB
Y
DY
Q
DIG
CE
CLK
Shared between
x & y Registers
SR
CIN
Figure 17: Virtex-II Slice (Top Half)
DS031_01_112502
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
20