XQ2V1000_1 Datasheet, PDF (77/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
QPro Virtex-II Pin Definitions
This section describes the pinouts for QPro Virtex-II devices
in the following packages:
• FG456: wire-bond fine-pitch BGA of 1.00 mm pitch
• BG575 and BG728: wire-bond BGA of 1.27 mm pitch
• CG717: wire-bond ceramic column grid of 1.27 mm
pitch
• CF1144: Ceramic flip-chip fine-pitch column grid of
1.00 mm pitch
Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards (see the QPro Virtex-II Data
Sheet). Global pins, including JTAG, configuration, and
power/ground pins, are listed at the end of each table.
Table 71 provides definitions for all pin types.
All QPro Virtex-II pinout tables are available on the
distribution CD-ROM, or on the web (at http://www.xilinx.com).
Pin Definitions
Table 71 provides a description of each pin type listed in QPro Virtex-II pinout tables.
Table 71: QPro Virtex-II Pin Definitions
Pin Name
Direction
Description
User I/O Pins
IO_LXXY_#
Input/Output
All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS, BLVDS,
LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
• IO indicates a user I/O pin.
• LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive
and negative sides of the differential pair.
• # indicates the bank number (0 through 7).
Dual-Function Pins
IO_LXXY_#/ZZZ
The dual-function pins are labelled “IO_LXXY_#/ZZZ”, where ZZZ can be one of the following
pins:
• Per Bank – VRP, VRN, or VREF
• Globally – GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 – D7, RDWR_B, or CS_B
With /ZZZ
DIN/D0, D1, D2, Input/Output
D3, D4, D5, D6,
D7
In SelectMAP mode, D0 through D7 are configuration data pins. These pins become user I/Os
after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after
configuration.
CS_B
Input
In SelectMAP mode, this is the active-Low Chip Select signal. This pin becomes a user I/O after
configuration, unless the SelectMAP port is retained.
RDWR_B
Input
In SelectMAP mode, this is the active-Low Write Enable signal. This pin becomes a user I/O after
configuration, unless the SelectMAP port is retained.
BUSY/DOUT Output
In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. This pin
becomes a user I/O after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a
daisy chain. This pin becomes a user I/O after configuration.
INIT_B
Bidirectional
(open-drain)
When Low, this pin indicates that the configuration memory is being cleared. When held Low, the
start of configuration is delayed. During configuration, a Low on this output indicates that a
configuration data error has occurred. This pin becomes a user I/O after configuration.
GCLKx (S/P)
Input/Output These are clock input pins that connect to Global Clock Buffers. These pins become regular user
I/Os when not needed for clocks.
VRP
Input
This pin is for the DCI voltage reference resistor of the P transistor (per bank).
VRN
Input
This pin is for the DCI voltage reference resistor of the N transistor (per bank).
ALT_VRP
Input
This is the alternative pin for the DCI voltage reference resistor of the P transistor.
ALT_VRN
Input
This is the alternative pin for the DCI voltage reference resistor of the N transistor.
V_REF
Input
These are input threshold voltage pins. They become user I/Os when an external threshold
voltage is not needed (per bank).
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
77