XQ2V1000_1 Datasheet, PDF (63/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Clock Distribution Switching Characteristics
Table 45: Clock Distribution Switching Characteristics
Description
Global Clock Buffer I input to O output
Global Clock Buffer S input Setup/Hold
to I1 an I2 inputs
Symbol
T_GIO
T_GSI/T_GIS
Speed Grade
-5
-4
0.52
0.59
0.61/ 0
0.70/ 0
Units
ns
ns
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 46). The values listed below are worst-
case. Precise values are provided by the timing analyzer.
Table 46: CLB Switching Characteristics
Description
Symbol
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
Incremental delay routing through transparent latch to XQ/YQ outputs
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
Minimum Pulse Width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)
Toggle Frequency (MHz) (for export control)
T_ILO
T_IF5
T_IF5X
T_IFXY
T_INAFX
T_INBFX
T_SOPSOP
T_IFNCTL
T_CKO
T_CKLO
T_DICK/T_CKDI
T_DYCK/T_CKDY
T_DXQK/T_CKDX
T_CECK/T_CKCE
T_SRCK/T_SCKR
T_CH
T_CL
T_RPW
T_RQ
F_TOG
Speed Grade
-5
-4
Units
0.39
0.44
ns
0.63
0.72
ns
0.83
0.95
ns
0.39
0.45
ns
0.28
0.32
ns
0.28
0.32
ns
0.38
0.44
ns
0.45
0.51
ns
0.50
0.57
ns
0.59
0.68
ns
0.33/–0.08 0.37/–0.09
ns
0.33/–0.08 0.37/–0.09
ns
0.33/–0.08 0.37/–0.09
ns
0.21/–0.07 0.24/–0.08
ns
0.23/–0.03 0.26/–0.03
ns
0.67
0.77
ns
0.67
0.77
ns
0.67
0.77
ns
1.17
1.34
ns
750
650
MHz
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
63