XQ2V1000_1 Datasheet, PDF (78/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Table 71: QPro Virtex-II Pin Definitions (Cont’d)
Pin Name
Dedicated Pins⁽¹⁾
Direction
Description
CCLK
Input/Output Configuration clock. Output in Master mode or Input in Slave mode.
PROG_B
Input
Active-Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up
resistor.
DONE
Input/Output
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin
indicates completion of the configuration process. As an input, a Low level on DONE can be
configured to delay the start-up sequence.
M2, M1, M0
Input
Configuration mode selection.
HSWAP_EN
Input
Enable I/O pullups during configuration.
TCK
Input
Boundary Scan Clock.
TDI
Input
Boundary Scan Data Input.
TDO
Output
Boundary Scan Data Output.
TMS
Input
Boundary Scan Mode Select.
PWRDWN_B
Input
Active-Low power-down pin (unsupported). Driving this pin Low can adversely affect device
(unsupported) operation and configuration. PWRDWN_B is internally pulled High, which is its default state. It
does not require an external pull-up.
Other Pins
DXN, DXP
N/A
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
V_BATT
RSVD
Input
N/A
Decryptor key memory backup supply. (Do not connect if battery is not used.)
Reserved pin – do not connect.
V_CCO
V_CCAUX
V_CCINT
GND
Input
Input
Input
Input
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V_CCAUX (independent of the bank V_CCO voltage).
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
78