XQ2V1000_1 Datasheet, PDF (68/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
QPro Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DCM
Table 54: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DCM
Description
Symbol
Device
Speed Grade
-5
-4
LVTTL Global Clock Input to Output delay using Output flip-flop,
12 mA, Fast Slew Rate, with DCM. For data output with different
standards, adjust the delays with the values shown in "IOB Output
Switching Characteristics Standard Adjustments," page 58.
Global Clock and OFF with DCM
T_ICKOFDCM
XQ2V1000
XQ2V3000
1.28
1.28
1.48
1.48
XQ2V6000
1.88
2.17
Units
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured with a 35 pF external capacitive load. The only time it is not 50% of V_CC threshold is with LVCMOS. For other I/O
standards and different loads, see Table 43, page 61.
3. DCM output jitter is included in the measurement.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DCM
Table 55: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DCM
Description
Symbol
Device
Speed Grade
-5
-4
LVTTL Global Clock Input to Output Delay using Output flip-flop,
12 mA, Fast Slew Rate, without DCM. For data output with different
standards, adjust the delays with the values shown in "IOB Output
Switching Characteristics Standard Adjustments," page 58.
Global Clock and OFF without DCM
T_ICKOF
XQ2V1000
4.28
4.62
XQ2V3000
4.43
5.10
XQ2V6000
5.38
5.93
Units
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V_CC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 43, page 61.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
68