XQ2V1000_1 Datasheet, PDF (22/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
X-Ref Target - Figure 20
A[4] ^(BX)
4
A[3:0]
D ^(BY)
WE ^(SR)
WCLK
4
RAM 32x1S
RAM
G[4:1] D
WG[4:1]
WS DI
WSG
WE0
WE
CK
WSF
F5MUX
WS DI
RAM _D
F[4:1]
WF[4:1]
DQ
Output
Registered
Output
(optional)
DS031_03_110100
Figure 20: Single-Port Distributed SelectRAM
(RAM32x1S)
X-Ref Target - Figure 21
RAM 16x1D
DPRA[3:0]
A[3:0]
D
4
4
(BY)
dual_port
RAM
G[4:1] D
WG[4:1]
WS DI
WSG
WE
CK
DPO
A[3:0]
4
dual_port
RAM
G[4:1] D
WG[4:1]
WS DI
SPO
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are available: ROM16x1, ROM32x1, ROM64x1,
ROM128x1, and ROM256x1. The ROM elements are
cascadable to implement wider or/and deeper ROM. ROM
contents are loaded at configuration. Table 14 shows the
number of LUTs occupied by each configuration.
Table 14: ROM Configuration
ROM
16 x 1
32 x 1
64 x 1
128 x 1
256 x 1
Number of LUTs
1
2
4
8 (1 CLB)
16 (2 CLBs)
Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a clock
input (CLK) and an optional clock enable, as shown in
Figure 22. A dynamic read access is performed through the 4-
bit address bus, A[3:0]. The configurable 16-bit shift register
cannot be set or reset. The read is asynchronous, however, the
storage element or flip-flop is available to implement a
synchronous read. The storage element should always be
used with a constant address. For example, when building an
8-bit shift register and configuring the addresses to point to the
seventh bit, the eighth bit can be the flip-flop. The overall
system performance is improved by using the superior clock-
to-out of the flip-flops.
X-Ref Target - Figure 22
SHIFTIN
SRLC16
A[3:0]
D(BY)
CE (SR)
CLK
SHIFT-REG
4 _A[4:1]
D
MC15
WS
DI
WSG
WE
CK
DQ
Output
Registered
Output
(optional)
WE
WCLK
(SR)
WSG
WE
CK
DS031_04_110100
Figure 21: Dual-Port Distributed SelectRAM
(RAM16x1D)
SHIFTOUT
DS031_05_110600
Figure 22: Shift Register Configurations
An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See
Figure 23, page 23.) Longer shift registers can be built with
dynamic access to any bit in the chain. The shift register
chaining and the MUXF5, MUXF6, and MUXF7 multiplexers
allow up to a 128-bit shift register with addressable access
to be implemented in one CLB.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
22