XQ2V1000_1 Datasheet, PDF (15/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require
termination to prevent reflections and maintain signal
integrity. High pin count packages (especially ball grid arrays)
can not accommodate external termination resistors.
Virtex-II XCITE DCI provides controlled impedance drivers
and on-chip termination for single-ended and differential
I/Os. This eliminates the need for external resistors, and
improves signal integrity. The DCI feature can be used on
any IOB by selecting one of the DCI I/O standards.
When applied to inputs, DCI provides input parallel
termination. When applied to outputs, DCI provides
controlled impedance drivers (series termination) or output
parallel termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external
reference resistors must be connected to two dual-function
pins on the bank. These resistors, the voltage reference of
the N transistor (VRN), and the voltage reference of the P
transistor (VRP) are shown in Figure 10.
X-Ref Target - Figure 10
1 Bank
DCI
DCI
DCI
DCI
VCCO
VRN
VRP
R_REF (1%)
R_REF (1%)
GND
DS031_50_101200
Figure 10: DCI in a Virtex-II Bank
When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50 Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25 Ω to 100 Ω). For all series and parallel
terminations listed in Table 11 and Table 12, the reference
resistors must have the same value for any given bank. One
percent resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors or half of the reference
resistors, and compensates for impedance changes due to
voltage and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
Controlled Impedance Drivers
(Series Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.
X-Ref Target - Figure 11
IOB
Z
Z
Virtex-II DCI
V_CCO = 3.3 V, 2.5 V, 1.8 V or 1.5 V _{DS031_51_110600}
Figure 11: Internal Series Termination
Table 11: SelectI/O-Ultra Controlled Impedance Buffers
V_CCO
3.3 V
DCI
LVDCI_33
DCI Half Impedance
LVDCI_DV2_33
2.5 V
LVDCI_25
LVDCI_DV2_25
1.8 V
LVDCI_18
LVDCI_DV2_18
1.5 V
LVDCI_15
LVDCI_DV2_15
Controlled Impedance Drivers
(Parallel Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
Table 12 lists the on-chip parallel terminations available in
Virtex-II devices. V_CCO must be set according to Table 8.
Note that there is a V_CCO requirement for GTL_DCI and
GTLP_DCI, due to the on-chip termination resistor.
Table 12: SelectI/O-Ultra Buffers with On-Chip Parallel
Termination
I/O Standard
SSTL3 Class I
SSTL3 Class II
SSTL2 Class I
SSTL2 Class II
External
Termination
SSTL3_I
SSTL3_II
SSTL2_I
SSTL2_II
On-Chip
Termination
SSTL3_I_DCI ⁽¹⁾
SSTL3_II_DCI ⁽¹⁾
SSTL2_I_DCI ⁽¹⁾
SSTL2_II_DCI ⁽¹⁾
HSTL Class I
HSTL_I
HSTL_I_DCI
HSTL Class II
HSTL_II
HSTL_II_DCI
HSTL Class III
HSTL_III
HSTL_III_DCI
HSTL Class IV
HSTL_IV
HSTL_IV_DCI
GTL
GTL
GTL_DCI
GTLP
GTLP
GTLP_DCI
Notes:
1. SSTL Compatible
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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