XQ2V1000_1 Datasheet, PDF (60/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Table 42: IOB Output Switching Characteristics Standard Adjustments (Cont’d)
Description
Symbol
Standard
Standard-specific adjustments for output delays
terminating at pads (based on standard capacitive
load, Csl)
T_{OLVCMOS18_F12}
T_{OLVCMOS18_F16}
T_{OLVCMOS15_S2}
T_{OLVCMOS15_S4}
T_{OLVCMOS15_S6}
T_{OLVCMOS15_S8}
T_{OLVCMOS15_S12}
T_{OLVCMOS15_S16}
T_{OLVCMOS15_F2}
T_{OLVCMOS15_F4}
T_{OLVCMOS15_F6}
T_{OLVCMOS15_F8}
T_{OLVCMOS15_F12}
T_{OLVCMOS15_F16}
T_{OLVDCI_33}
T_{OLVDCI_25}
T_{OLVDCI_18}
T_{OLVDCI_15}
T_{OLVDCI_DV2_33}
T_{OLVDCI_DV2_25}
T_{OLVDCI_DV2_18}
T_{OLVDCI_DV2_15}
T_{OGTL_DCI}
T_{OGTLP_DCI}
T_{OHSTL_I_DCI}
T_{OHSTL_II_DCI}
T_{OHSTL_III_DCI}
T_{OHSTL_IV_DCI}
T_{OHSTL_I_DCI_18}
T_{OHSTL_II_DCI_18}
T_{OHSTL_III_DCI_18}
T_{OHSTL_IV_DCI_18}
T_{OSSTL2_I_DCI}
T_{OSSTL2_II_DCI}
T_{OSSTL3_I_DCI}
T_{OSSTL3_II_DCI}
12 mA
16 mA
LVCMOS15, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
LVCMOS15, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
Speed Grade
-5
-4
0.27 0.30
0.23 0.26
19.55 21.50
13.17 14.48
12.42 13.66
10.06 11.06
9.32 10.25
8.46 9.31
5.25 5.78
2.07 2.27
1.51 1.66
0.96 1.05
0.77 0.84
0.69 0.75
0.77 0.84
0.80 0.88
0.87 0.95
1.88 2.06
0.12 0.13
0.03 0.03
0.43 0.48
1.23 1.36
–0.32 –0.35
–0.16 –0.17
0.23 0.26
0.06 0.07
–0.18 –0.20
–0.47 –0.52
0.05 0.06
–0.03 –0.03
–0.14 –0.16
–0.42 –0.47
0.13 0.14
–0.10 –0.11
0.16 0.17
0.08 0.09
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
60