XQ2V1000_1 Datasheet, PDF (30/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

R
QPro Virtex-II 1.5V Platform FPGAs
Table 19: Dual-Port Mode Configurations
Port A
16K x 1
16K x 1
Port B
16K x 1
8K x 2
Port A
8K x 2
8K x 2
Port B
8K x 2
4K x 4
Port A
4K x 4
4K x 4
Port B
4K x 4
2K x 9
Port A
2K x 9
2K x 9
Port B
2K x 9
1K x 18
Port A
1K x 18
1K x 18
Port B
1K x 18
512 x 36
Port A
512 x 36
Port B
512 x 36
16K x 1
4K x 4
8K x 2
2K x 9
4K x 4
1K x 18
2K x 9
512 x 36
16K x 1
2K x 9
8K x 2
1K x 18
4K x 4
512 x 36
16K x 1
1K x 18
8K x 2
512 x 36
16K x 1
512 x 36
X-Ref Target - Figure 31
18 Kbit Block SelectRAM
DIA
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DOA
DOPA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
DOB
DOPB
DS031_11_071602
Figure 31: 18 Kbit Block SelectRAM in Dual-Port Mode
Port Aspect Ratios
Table 20 shows the depth and the width aspect ratios for the
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Table 20: 18 Kbit Block SelectRAM Port Aspect Ratio
Width Depth Address Bus Data Bus Parity Bus
1
16,384 ADDR[13:0]
DATA[0]
N/A
2
8,192 ADDR[12:0] DATA[1:0]
N/A
4
4,096 ADDR[11:0] DATA[3:0]
N/A
9
2,048 ADDR[10:0] DATA[7:0] Parity[0]
18
1,024
ADDR[9:0] DATA[15:0] Parity[1:0]
36
512
ADDR[8:0] DATA[31:0] Parity[3:0]
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully
synchronous. An address is presented, and the read
operation is enabled by control signals WEA and WEB in
addition to ENA or ENB. Then, depending on clock polarity,
a rising or falling clock edge causes the stored data to be
loaded into output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configuration:
• WRITE_FIRST
The WRITE_FIRST option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in Figure 32, page 31.
• READ_FIRST
The READ_FIRST option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in Figure 33, page 31.
• NO_CHANGE
The NO_CHANGE option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as NO_CHANGE, only a read operation
loads a new value in the output register DO, as shown in
Figure 34, page 31.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
30