XQ2V1000_1 Datasheet, PDF (53/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
QPro Virtex-II Switching Characteristics
Switching characteristics in this document are specified on
a per-speed-grade basis and can be designated as
Advance, Preliminary, or Production. Each designation is
defined as follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design
specifications are frozen. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device. Table 38 correlates the current status of each QPro
Virtex-II device with a corresponding speed grade designation.
Table 38: QPro Virtex-II Device Speed Grade Designations
Device
Speed Grade Designations
Advance Preliminary Production
XQ2V1000
-4(N)
XQ2V3000
-4(M,N)
XQ2V6000
-5(I), -4(I,M)
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the Xilinx static timing analyzer
and back-annotate to the simulation net list. Unless
otherwise noted, values apply to all QPro Virtex-II devices.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
53