XQ2V1000_1 Datasheet, PDF (3/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

R
QPro Virtex-II 1.5V Platform FPGAs
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with
various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic
designs. As shown in Figure 1, the programmable device is
comprised of input/output blocks (IOBs) and internal
configurable logic blocks (CLBs).
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
The internal configurable logic includes four major elements
organized in a regular array:
• Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
X-Ref Target - Figure 1
Global Clock Mux
• Block SelectRAM memory modules provide large
18 Kbit storage elements of dual-port RAM.
• Multiplier blocks are 18-bit x 18-bit dedicated multipliers.
• DCM (Digital Clock Manager) blocks provide self-
calibrating, fully digital solutions for clock distribution
delay compensation, clock multiplication and division,
coarse- and fine-grained clock phase shifting.
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
DCM
DCM
IOB
Configurable Logic
Programmable I/Os
CLB Block SelectRAM
Multiplier
DS031_28_100900
Figure 1: Virtex-II Architecture Overview
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
3