XQ2V1000_1 Datasheet, PDF (65/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Multiplier Switching Characteristics
Table 49 and Table 50 provide timing information for QPro Virtex-II multiplier blocks, available in stepping revisions of QPro
Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales
representative.
Table 49: Enhanced Multiplier Switching Characteristics
Description
Propagation Delay to Output Pin
Input to Pin 35
Input to Pin 34
Input to Pin 33
Input to Pin 32
Input to Pin 31
Input to Pin 30
Input to Pin 29
Input to Pin 28
Input to Pin 27
Input to Pin 26
Input to Pin 25
Input to Pin 24
Input to Pin 23
Input to Pin 22
Input to Pin 21
Input to Pin 20
Input to Pin 19
Input to Pin 18
Input to Pin 17
Input to Pin 16
Input to Pin 15
Input to Pin 14
Input to Pin 13
Input to Pin 12
Input to Pin 11
Input to Pin 10
Input to Pin 9
Input to Pin 8
Input to Pin 7
Input to Pin 6
Input to Pin 5
Input to Pin 4
Input to Pin 3
Input to Pin 2
Input to Pin 1
Input to Pin 0
Symbol
T_{MULT_P35}
T_{MULT_P34}
T_{MULT_P33}
T_{MULT_P32}
T_{MULT_P31}
T_{MULT_P30}
T_{MULT_P29}
T_{MULT_P28}
T_{MULT_P27}
T_{MULT_P26}
T_{MULT_P25}
T_{MULT_P24}
T_{MULT_P23}
T_{MULT_P22}
T_{MULT_P21}
T_{MULT_P20}
T_{MULT_P19}
T_{MULT_P18}
T_{MULT_P17}
T_{MULT_P16}
T_{MULT_P15}
T_{MULT_P14}
T_{MULT_P13}
T_{MULT_P12}
T_{MULT_P11}
T_{MULT_P10}
T_{MULT_P9}
T_{MULT_P8}
T_{MULT_P7}
T_{MULT_P6}
T_{MULT_P5}
T_{MULT_P4}
T_{MULT_P3}
T_{MULT_P2}
T_{MULT_P1}
T_{MULT_P0}
Speed Grade
-5
-4
5.14
5.91
5.03
5.79
4.93
5.66
4.82
5.54
4.71
5.42
4.61
5.29
4.50
5.17
4.39
5.05
4.28
4.92
4.18
4.80
4.07
4.68
3.96
4.56
3.86
4.43
3.75
4.31
3.64
4.19
3.54
4.06
3.43
3.94
3.32
3.82
3.21
3.69
3.11
3.57
3.00
3.45
2.89
3.33
2.79
3.20
2.68
3.08
2.57
2.96
2.47
2.83
2.36
2.71
2.25
2.59
2.14
2.46
2.04
2.34
1.93
2.22
1.82
2.10
1.72
1.97
1.61
1.85
1.50
1.73
1.40
1.60
Units
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DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
65