XQ2V1000_1 Datasheet, PDF (62/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Table 44: Standard Capacitive Loads
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI 33 MHZ 3.3V
PCI 66 MHz 3.3V
PCI–X 133 MHz 3.3V
GTL
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
AGP
Standard
Csl (pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
10
0
0
10
10
10
10
10
10
10
10
10
Notes:
1. I/O parameter measurements are made with the capacitance values shown above.
2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
3. Use of IBIS models results in a more accurate prediction of the propagation delay:
♦ Model the output in an IBIS simulation into the standard capacitive load.
♦ Record the relative time to the VOH or VOL transition of interest.
♦ Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS models
for driven devices.
♦ Record the results from the new simulation.
♦ Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should be
added or subtracted from the value above to predict the actual delay.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
62