XQ2V1000_1 Datasheet, PDF (72/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Output Clock Jitter
Table 60: Output Clock Jitter
Description
Clock Synthesis Period Jitter
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Symbol
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
Constraints
Speed Grade
-5
-4
Units
±100 ±100
ps
±150 ±150
ps
±150 ±150
ps
±150 ±150
ps
±200 ±200
ps
±150 ±150
ps
±300 ±300
ps
Note 1 Note 1 ps
Notes:
1. Values for this parameter are available at http://www.xilinx.com.
Output Clock Phase Alignment
Table 61: Output Clock Phase Alignment
Description
Symbol
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs
All CLK* outputs
Duty Cycle Precision
DLL outputs⁽¹⁾
CLKFX outputs
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
CLKOUT_DUTY_CYCLE_DLL⁽²⁾
CLKOUT_DUTY_CYCLE_FX
Constraints
Speed Grade
-5
-4
Units
±50
±50
ps
±140 ±140
ps
±150 ±150
ps
±100 ±100
ps
Notes:
1. The term DLL outputs is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION
= TRUE.
3. Specification also applies to PSCLK.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
72