XQ2V1000_1 Datasheet, PDF (29/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
18 Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures
implemented in CLBs. Each Virtex-II block SelectRAM is an
18 Kbit true dual-port RAM with two independently clocked
and independently controlled synchronous ports that
access a common storage area. Both ports are functionally
identical. CLK, EN, WE, and SSR polarities are defined
through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for writes) and Data/parity
data outputs (for reads).
Operation is synchronous. The block SelectRAM behaves
like a register. Control, address, and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various
configurations, including single- and dual-port RAM and
various data/address aspect ratios. Supported memory
configurations for single- and dual-port modes are shown in
Table 18.
Table 18: Dual- and Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of 9-bit, 18-bit,
and 36-bit widths is the ability to store a parity bit for every
eight bits. Parity bits must be generated or checked
externally in user logic. In such cases, the width is viewed
as 8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored
and behave exactly as the other bits, including the timing
parameters. Video applications can use the 9-bit ratio of
Virtex-II block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in Figure 30. Input data bus and output data
bus widths are identical.
X-Ref Target - Figure 30
18 Kbit Block SelectRAM
DI
DIP
ADDR
WE
EN
SSR
CLK
DO
DOP
DS031_10_071602
Figure 30: 18 Kbit Block SelectRAM Memory in Single-
Port Mode
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be
configured independently, providing built-in bus-width
conversion (Table 19, page 30 illustrates the different
configurations available on Ports A and B).
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is
accessible from Port A or B. If both ports are configured in
either 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations,
the 16 Kbit block is accessible from Port A or Port B. All
other configurations result in one port having access to an
18 Kbit memory block and the other port having access to a
16 Kbit subset of the memory block equal to 16 Kbits.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in Table 31, page 30. The two ports have
independent inputs and outputs and are independently
clocked.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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