XQ2V1000_1 Datasheet, PDF (45/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Configuration
Virtex-II devices are configured by loading application-
specific configuration data into the internal configuration
memory. Configuration is carried out using a subset of the
device pins, some of which are dedicated, while others can
be re-used as general purpose inputs and outputs once
configuration is complete.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M2, M1, and M0 are dedicated pins. An additional pin,
HSWAP_EN, is used in conjunction with the mode pins to
select whether user I/O pins have pull-ups during
configuration. By default, HSWAP_EN is tied High (internal
pull-up), which shuts off the pull-ups on the user I/O pins
during configuration. When HSWAP_EN is tied Low, user
I/Os have pull-ups during configuration. Other dedicated
pins are CCLK (the configuration clock pin), DONE,
PROG_B, and the boundary-scan pins: TDI, TDO, TMS,
and TCK. Depending on the configuration mode chosen,
CCLK can be an output generated by the FPGA, or an input
accepting an externally generated clock. The configuration
pins and boundary-scan pins are independent of the V_CCO.
The auxiliary power supply (V_CCAUX) of 3.3V is used for
these pins. All configuration pins are LVTTL 12 mA. (See
"QPro Virtex-II DC Characteristics".)
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected, then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.
Configuration Modes
Virtex-II supports the following five configuration modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-Scan mode (IEEE 1532/IEEE 1149)
A detailed description of configuration modes is provided in
[Ref 1].
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy chained for configuration from
a single source. After a particular FPGA has been
configured, the data for the next device is routed internally
to the DOUT pin. The data on the DOUT pin changes on the
rising edge of CCLK.
Slave-serial mode is selected by applying <111> to the
mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left
unconnected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is
the Virtex-II FPGA device that drives the configuration clock
on the CCLK pin to a Xilinx Serial PROM, which in turn
feeds bit-serial data to the DIN input. The FPGA accepts
this data on each rising CCLK edge. After the FPGA has
been loaded, the data for the next device in a daisy chain is
presented on the DOUT pin after the rising CCLK edge.
The interface is identical to slave serial except that an
internal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK, which always starts at a slow default frequency.
Configuration bits then switch CCLK to a higher frequency
for the remainder of the configuration.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II FPGA device with a
BUSY flag controlling the flow of data. An external data
source provides a byte stream, CCLK, an active-Low Chip
Select (CS_B) signal, and a Write signal (RDWR_B). If BUSY
is asserted (High) by the FPGA, the data must be held until
BUSY goes Low. Data can also be read using the SelectMAP
mode. If RDWR_B is asserted, configuration data is read out
of the FPGA as part of a readback operation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the
persist option.
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and can be made to start-up
simultaneously. To configure multiple devices in this way,
wire the individual CCLK, Data, RDWR_B, and BUSY pins
of all the devices in parallel. The individual devices are
loaded separately by deasserting the CS_B pin of each
device in turn and writing the appropriate data.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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