XQ2V1000_1 Datasheet, PDF (16/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

R
QPro Virtex-II 1.5V Platform FPGAs
Figure 12 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O
standards. For a complete list, see the [Ref 1].
X-Ref Target - Figure 12
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
Conventional
VCCO/2
R
Z0
VCCO/2 VCCO/2
R
R
Z0
VCCO
R
Z0
VCCO
VCCO
R
R
Z0
DCI Transmit
Conventional
Receive
Virtex-II DCI
VCCO/2
R
Z0
VCCO
2R
2R
Virtex-II DCI
VCCO/2
R
Z0
Virtex-II DCI
VCCO
R
Z0
VCCO
R
Virtex-II DCI
VCCO
R
Z0
Conventional
Transmit
DCI Receive
VCCO
2R
Z0
2R
Virtex-II DCI
VCCO/2
R
Z0
VCCO
2R
2R
Virtex-II DCI
VCCO
R
Z0
Virtex-II DCI
VCCO
R
Z0
VCCO
R
Virtex-II DCI
DCI Transmit
DCI Receive
Virtex-II DCI
VCCO
2R
Z0
2R
VCCO
2R
VCCO
2R
Z0
2R
2R
Virtex-II DCI Virtex-II DCI
Virtex-II DCI Virtex-II DCI
VCCO
R
Z0
VCCO
VCCO
R
R
Z0
Virtex-II DCI Virtex-II DCI
Virtex-II DCI
Bidirectional
N/A
Reference
Resistor
Recommended
Z0
VRN = VRP = R = Z0
50 Ω
VCCO
2R
2R
VCCO
2R
Z0
2R
Virtex-II DCI
Virtex-II DCI
N/A
VCCO
R
VCCO
R
Z0
Virtex-II DCI
Virtex-II DCI
VRN = VRP = R = Z0
VRN = VRP = R = Z0
VRN = VRP = R = Z0
50 Ω
50 Ω
Figure 12: HSTL DCI Usage Examples
50 Ω
DS031_65a_100201
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
16