XQ2V1000_1 Datasheet, PDF (26/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
large, flexible SOP chains. One input of each ORCY is
connected through the fast SOP chain to the output of the
previous ORCY in the same slice row. The second input is
X-Ref Target - Figure 26
connected to the output of the top MUXCY in the same slice,
as shown in Figure 26.
LUTs and MUXCYs can implement large AND gates or other
combinatorial logic functions. Figure 27 illustrates LUT and
MUXCY resources configured as a 16-input AND gate.
ORCY
ORCY
4 _LUT
4 _LUT
MUXCY
4 _LUT
Slice 1
MUXCY
4 _LUT
MUXCY
Slice 3
MUXCY
4 _LUT
4 _LUT
ORCY
MUXCY
4 _LUT
Slice 1
MUXCY
4 _LUT
ORCY
SOP
MUXCY
Slice 3
MUXCY
X-Ref Target - Figure 27
4 _LUT
4 _LUT
4
MUXCY
Slice 0
4
MUXCY
V_CC
LUT
LUT
MUXCY
Slice 2
MUXCY
V_CC
CLB
4 _LUT
4 _LUT
MUXCY
4 _LUT
Slice 0
MUXCY
4 _LUT
V_CC
Figure 26: Horizontal Cascade Chain
MUXCY
Slice 2
MUXCY
V_CC
CLB
ds031_64_110300
OUT
4
LUT
4
LUT
MUXCY
0
1
“0”
Slice
MUXCY
0
1
“0”
16
AND
OUT
4
LUT
4
LUT
MUXCY
0
1
“0”
Slice
MUXCY
0
1
VCC
DS031_41_110600
Figure 27: Wide-Input AND Gate (16 Inputs)
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
26