XQ2V1000_1 Datasheet, PDF (54/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in "IOB Input Switching Characteristics Standard Adjustments," page 55.
Table 39: IOB Input Switching Characteristics
Description
Symbol
Device
Propagation Delays
Pad to I output, no delay
Pad to I output, with delay
T_IOPI
T_IOPID
All
XQ2V1000
XQ2V3000
XQ2V6000
Pad to output IQ via transparent latch, no delay
Pad to output IQ via transparent latch, with delay
T_IOPLI
T_IOPLID
All
XQ2V1000
XQ2V3000
XQ2V6000
Clock CLK to output IQ
T_IOCKIQ
All
Setup and Hold Times with Respect to Clock at IOB Input Register
Pad, no delay
Pad, with delay
T_IOPICK/T_IOICKP
T_IOPICKD/T_IOICKPD
All
XQ2V1000
XQ2V3000
XQ2V6000
ICE input
SR input (IFF, synchronous)
Set/Reset Delays
T_IOICECK/T_IOCKICE
All
T_IOSRCKI
All
SR input to IQ (asynchronous)
GSR to output IQ
T_IOSRIQ
All
T_GSRQ
All
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 43.
Speed Grade
-5
-4
0.76
0.88
2.11
2.43
2.16
2.49
2.31
2.66
0.91
1.05
3.55
4.09
3.65
4.20
3.95
4.55
0.67
0.77
0.92/–0.39
3.57/–2.24
3.67/–2.31
3.97/–2.52
0.21/ 0.04
0.27
1.06/–0.45
4.10/–2.58
4.22/–2.66
4.56/–2.90
0.24/ 0.04
0.34
1.22
1.40
5.98
6.88
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
54