XQ2V1000_1 Datasheet, PDF (42/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Hierarchical Routing Resources
Most Virtex-II signals are routed using the global routing
resources, which are located in horizontal and vertical
routing channels between each switch matrix. As shown in
Figure 50, Virtex-II devices have fully buffered
programmable interconnections, with a number of
resources counted between any two adjacent switch matrix
rows or columns. Fanout has minimal impact on the
performance of each net.
In Figure 50:
• Long lines are bidirectional wires that distribute signals
across the device. Vertical and horizontal long lines
span the full height and width of the device.
X-Ref Target - Figure 50
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
• Hex lines route signals to every third or sixth block away in
all four directions. Organized in a staggered pattern, hex
lines can only be driven from one end. Hex-line signals
can be accessed either at the endpoints or at the midpoint
(three blocks from the source).
• Double lines route signals to every first or second block
away in all four directions. Organized in a staggered
pattern, double lines can be driven only at their
endpoints. Double-line signals can be accessed either
at the endpoints or at the midpoint (one block from the
source).
• Direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
Fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
16 Direct Connections
(total in all four directions)
8 Fast Connects
Figure 50: Hierarchical Routing Resources
DS031_60_110200
Dedicated Routing
In addition to the global and local routing resources,
dedicated signals are available:
• There are eight global clock nets per quadrant (see
"Global Clock Multiplexer Buffers").
• Horizontal routing resources are provided for on-chip 3-
state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row.
(See "3-State Buffers".)
• Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
"CLB/Slice Configurations".)
• One dedicated SOP chain per slice row (two per CLB
row) propagates ORCY output logic signals horizontally
to the adjacent slice. (See "Sum of Products".)
• One dedicated shift chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See "Shift Registers".)
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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