XQ2V1000_1 Datasheet, PDF (43/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated
Synthesis Environment (ISE) development systems, which
support advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.
As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technologies
in the programmable logic design process. Xilinx
development systems are available in a number of easy to
use configurations, collectively known as the ISE Series.
ISE Alliance
The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry
standard data formats and netlists, these stable, flexible
products enable Alliance EDA partners to deliver their best
design automation capabilities to Xilinx customers, along
with the time to market benefits of ProActive Timing Closure.
ISE Foundation
The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design
environment. An intuitive project navigator, as well as
powerful HDL design and two HDL synthesis tools, ensure
that high-quality results are achieved quickly and easily. The
ISE Foundation product includes:
• State Diagram entry using Xilinx StateCAD
• Automatic HDL Testbench generation using Xilinx
HDLBencher
• HDL Simulation using ModelSim XE
Design Flow
Virtex-II design flow proceeds as follows:
• Design Entry
• Synthesis
• Implementation
• Verification
Most programmable logic designers iterate through these
steps several times in the process of completing a design.
Design Entry
All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental,
modular, and Intellectual Property (IP) design techniques.
When properly used, these techniques further accelerate
the logic design process.
To enable designers to leverage existing investments in
EDA tools and to ensure high-performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:
• Aldec
• Cadence
• Exemplar
• Mentor Graphics
• Model Technology
• Synopsys
• Synplicity
Complete information on Alliance Series partners and their
associated design flows is available at http://www.xilinx.com
on the Xilinx Alliance Series web page.
The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution, enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design
capabilities include a color-coded HDL editor with
integrated language templates, state diagram entry, and
Core generation capabilities.
Synthesis
The ISE Alliance product is engineered to support
advanced design flows with the industry's best synthesis
tools. Advanced design methodologies include:
• Physical Synthesis
• Incremental synthesis
• RTL floorplanning
• Direct physical mapping
The ISE Foundation product seamlessly integrates
synthesis capabilities purchased directly from Exemplar,
Synopsys, and Synplicity. In addition, it includes the
capabilities of Xilinx Synthesis Technology.
A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply
alternative sets of optimization techniques on designs,
helping to ensure that designers can meet even the
toughest timing requirements.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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