XQ2V1000_1 Datasheet, PDF (56/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Table 40: IOB Input Switching Characteristics Standard Adjustments (Cont’d)
Description
Symbol
Standard
Standard-specific data input delay adjustments
T_{IHSTL_I_DCI}
T_{IHSTL_II_DCI}
T_{IHSTL_III_DCI}
T_{IHSTL_IV_DCI}
T_{IHSTL_I_DCI_18}
T_{IHSTL_II_DCI_18}
T_{IHSTL_III_DCI_18}
T_{IHSTL_IV_DCI_18}
T_{ISSTL2_I_DCI}
T_{ISSTL2_II_DCI}
T_{ISSTL3_I_DCI}
T_{ISSTL3_II_DCI}
T_{ILDT_25}
T_{IULVDS_25}
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 43.
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LDT_25
ULVDS_25
Speed Grade
-5
-4
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.42
0.48
0.35
0.40
0.35
0.40
0.49
0.56
0.49
0.56
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
56