XQ2V1000_1 Datasheet, PDF (12/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Figure 7 shows the SSTL2, SSTL3, and HSTL configurations.
HSTL can sink current up to 48 mA. (HSTL IV)
X-Ref Target - Figure 7
VCCO
OBUF
Clamp
Diode
PAD
VREF
VCCAUX = 3.3V
VCCINT = 1.5V
DS031_24_100900
Figure 7: SSTL or HSTL SelectI/O-Ultra Standards
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Virtex-II
devices use two memory cells to control the configuration of an
I/O as an input. This is to reduce the probability of an I/O
configured as an input from flipping to an output when
subjected to a single event upset (SEU) in space applications.
Prior to configuration, all outputs not involved in
configuration are forced into their high-impedance state.
The pull-down resistors and the weak-keeper circuits are
inactive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
driven High, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is driven Low, the pull-up resistors
are activated on user I/O pins.
All Virtex-II IOBs support IEEE 1149.1 compatible
Boundary-Scan testing.
Input Path
The Virtex-II IOB input path routes input signals directly to
internal logic and/or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II device, and when
used, ensures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V_REF. The need to supply V_REF imposes
constraints on which standards can be used in the same
bank (see "I/O Banking").
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and/or the 3-state
signal can be routed to the buffer directly from the internal
logic or through an output/3-state flip-flop or latch, or
through the DDR output/3-state registers.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most
signaling standards, the output High voltage depends on an
externally supplied V_CCO voltage. The need to supply V_CCO
imposes constraints on which standards can be used in the
same bank (see "I/O Banking").
I/O Banking
Some of the I/O standards described above require V_CCO
and V_REF voltages. These voltages are externally supplied
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in Figure 8 and Figure 9, page 13.
Each bank has multiple V_CCO pins, all of which must be
connected to the same voltage. This voltage is determined
by the output standards in use.
X-Ref Target - Figure 8
Bank 0
Bank 1
Bank 5
Bank 4
ug002_c2_014_112900
Figure 8: Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS, FG, & BG)
Some input standards require a user-supplied threshold
voltage (V_REF), and certain user-I/O pins are automatically
configured as V_REF inputs. Approximately one in six of the
I/O pins in the bank assume this role.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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