XQ2V1000_1 Datasheet, PDF (71/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Input Clock Tolerances
Table 59: Input Clock Tolerances
Description
Symbol
Constraints
F_CLKIN
Input Clock Low/High Pulse Width
PSCLK
PSCLK_PULSE
PSCLK and CLKIN⁽²⁾
PSCLK_PULSE and
CLKIN_PULSE
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_CYC_JITT_DLL_LF
CLKIN (using CLKFX outputs)⁽²⁾ CLKIN_CYC_JITT_FX_LF
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_CYC_JITT_DLL_HF
CLKIN (using CLKFX outputs)⁽²⁾ CLKIN_CYC_JITT_FX_HF
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_PER_JITT_DLL_LF
CLKIN (using CLKFX outputs)⁽²⁾ CLKIN_PER_JITT_FX_LF
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_PER_JITT_DLL_HF
CLKIN (using CLKFX outputs)⁽²⁾ CLKIN_PER_JITT_FX_HF
Feedback Clock Path Delay Variation
CLKFB off-chip feedback
CLKFB_DELAY_VAR_EXT
< 1 MHz
1 – 10 MHz
10 – 25 MHz
25 – 50 MHz
50 – 100 MHz
100 – 150 MHz
150 – 200 MHz
200 – 250 MHz
250 – 300 MHz
300 – 350 MHz
350 – 400 MHz
> 400 MHz
Speed Grade
-5
-4
Min Max Min Max
Units
25.00
25.00
ns
25.00
25.00
ns
10.00
10.00
ns
5.00
5.00
ns
3.00
3.00
ns
2.40
2.40
ns
2.00
2.00
ns
1.80
1.80
ns
1.50
1.50
ns
1.30
1.30
ns
1.15
1.15
ns
1.05
1.05
ns
±300
±300
±300 ps
±300 ps
±150
±150
±150 ps
±150 ps
±1
±1
ns
±1
±1
ns
±1
±1
ns
±1
±1
ns
±1
±1
ns
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the DCM phase shift feature is used and the CLKIN frequency > 200 MHz, the CLKIN duty cycle must be within ±5% (45/55 to 55/45).
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
71