XQ2V1000_1 Datasheet, PDF (39/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Phase Shifting
The DCM provides additional control over clock skew
through either coarse- or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the PHASE_SHIFT value can also be
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active. Figure 47 illustrates the effects of fine-phase
shifting. For more information on DCM features, see [Ref 1].
Table 26 lists fine-phase shifting control pins, when used in
variable mode.
Table 26: Fine-Phase Shifting Control Pins
Control Pin Direction
Function
PSINCDEC
in
Increment or decrement
PSEN
in
Enable ± phase shift
PSCLK
in
Clock for phase shift
PSDONE
out
Active when completed
Two separate components of the phase shift range must be
understood:
• PHASE_SHIFT attribute range
• FINE_SHIFT_RANGE DCM timing parameter range
X-Ref Target - Figure 47
CLKIN
CLKOUT_PHASE_SHIFT
= NONE
CLKFB
The PHASE_SHIFT attribute is the numerator in the
following equation:
Phase Shift (ns) =
(PHASE_SHIFT/256) × PERIOD_CLKIN
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this
absolute range is guaranteed to be as specified under
"DCM Timing Parameters".
Absolute range (fixed mode) = ± FINE_SHIFT_RANGE
Absolute range (variable mode) = ±
FINE_SHIFT_RANGE/2
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from –255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after
configuration, the entire delay line is available for insertion
into either the CLKIN or CLKFB path (to create either
positive or negative skew).
Taking both of these components into consideration, the
following are some usage examples:
• If PERIOD_CLKIN = 2 × FINE_SHIFT_RANGE, then
PHASE_SHIFT in fixed mode is limited to ± 128, and in
variable mode it is limited to ± 64.
• If PERIOD_CLKIN = FINE_SHIFT_RANGE, then
PHASE_SHIFT in fixed mode is limited to ± 255, and in
variable mode it is limited to ± 128.
• If PERIOD_CLKIN ≤ 0.5 × FINE_SHIFT_RANGE, then
PHASE_SHIFT is limited to ± 255 in either mode.
CLKIN
CLKOUT_PHASE_SHIFT
= FIXED
CLKFB
(PS/256) x PERIODCLKIN
(PS negative)
(PS/256) x PERIODCLKIN
(PS positive)
CLKIN
CLKOUT_PHASE_SHIFT
= VARIABLE
CLKFB
(PS/256) x PERIODCLKIN
(PS negative)
(PS/256) x PERIODCLKIN
(PS positive)
Figure 47: Fine-Phase Shifting Effects
DS031_48_101201
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
39