XQ2V1000_1 Datasheet, PDF (50/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult [Ref 2] for detailed information on power distribution
system design.
V_CCAUX powers critical resources in the FPGA. Thus,
V_CCAUX is especially susceptible to power supply noise.
Changes in V_CCAUX voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per
millisecond. Techniques to help reduce jitter and period
distortion are provided in Xilinx Answer Record 13756,
available at www.support.xilinx.com.
V_CCAUX can share a power plane with 3.3V V_CCO, but only if
V_CCO does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to [Ref 3] to
determine the number of simultaneously switching outputs
allowed per bank at the package level.
DC Input and Output Levels
Values for V_IL and V_IH are recommended input voltages.
Values for I_OL and I_OH are guaranteed over the
recommended operating conditions at the V_OL and V_OH test
points. Only selected standards are tested. These are
chosen to ensure that all standards meet their
specifications. The selected standards are tested at
minimum V_CCO with the respective V_OL and V_OH voltage
levels shown. Other standards are sample tested.
Table 36: DC Input and Output Levels
Input/Output
Standard
LVTTL⁽¹⁾
V, Min
–0.5
V_IL
V, Max
0.8
V_IH
V, Min
2.0
V, Max
3.6
V_OL
V, Max
0.4
V_OH
V, Min
2.4
I_OL
I_OH
mA
mA
24
–24
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
0.8
0.7
35% V_CCO
35% V_CCO
30% V_CCO
30% V_CCO
Note 2
2.0
1.7
65% V_CCO
65% V_CCO
50% V_CCO
50% V_CCO
Note 2
3.6
2.7
1.95
1.7
V_CCO + 0.5
V_CCO + 0.5
Note 2
0.4
0.4
0.4
0.4
10% V_CCO
10% V_CCO
Note 2
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
90% V_CCO
90% V_CCO
Note 2
24
24
16
16
Note 2
Note 2
Note 2
–24
–24
–16
–16
Note 2
Note 2
Note 2
GTLP
GTL
HSTL I
HSTL II
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
AGP
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V_REF – 0.1
V_REF – 0.05
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.2
V_REF – 0.2
V_REF – 0.15
V_REF – 0.15
V_REF – 0.2
V_REF + 0.1
V_REF + 0.05
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
V_REF + 0.2
V_REF + 0.2
V_REF + 0.15
V_REF + 0.15
V_REF + 0.2
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
0.6
0.4
0.4
0.4
0.4
0.4
V_REF – 0.6
V_REF – 0.8
V_REF – 0.65
V_REF – 0.80
10% V_CCO
n/a
n/a
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_REF + 0.6
V_REF + 0.8
V_REF + 0.65
V_REF + 0.80
90% V_CCO
36
40
8
16
24
48
8
16
7.6
15.2
Note 2
n/a
n/a
–8
–16
–8
–8
–8
–16
–7.6
–15.2
Note 2
Notes:
1. V_OL and V_OH for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.
2. Tested according to the relevant specifications.
3. LVTTL and LVCMOS inputs have approximately 100 mV of hysteresis.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
50