XQ2V1000_1 Datasheet, PDF (58/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Table 42: IOB Output Switching Characteristics Standard Adjustments
Description
Symbol
Standard
Output Delay Adjustments
Standard-specific adjustments for output delays
terminating at pads (based on standard capacitive
load, Csl)
T_{OLVTTL_S2}
T_{OLVTTL_S4}
T_{OLVTTL_S6}
T_{OLVTTL_S8}
T_{OLVTTL_S12}
T_{OLVTTL_S16}
T_{OLVTTL_S24}
T_{OLVTTL_F2}
T_{OLVTTL_F4}
T_{OLVTTL_F6}
T_{OLVTTL_F8}
T_{OLVTTL_F12}
T_{OLVTTL_F16}
T_{OLVTTL_F24}
T_{OLVDS_25}
T_{OLVDS_33}
T_{OLVDSEXT_25}
T_{OLVDSEXT_33}
T_{OLDT_25}
T_{OBLVDS_25}
T_{OULVDS_25}
T_{OLVPECL_33}
T_{OPCI33_3}
T_{OPCI66_3}
T_OPCIX
T_OGTL
T_OGTLP
T_{OHSTL_I}
T_{OHSTL_II}
T_{OHSTL_III}
T_{OHSTL_IV}
T_{OHSTL_I_18}
T_{OHSTL_II_18}
T_{OHSTL_III_18}
T_{OHSTL_IV_18}
T_{OSSTL2_I}
T_{OSSTL2_II}
LVTTL, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVTTL, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVDS
LVDS
LVDS
LVDS
LDT
BLVDS
ULVDS
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI–X, 133 MHz, 3.3V
GTL
GTLP
HSTL I
HSTL II
HSTL III
HSTL IV
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
SSTL2 I
SSTL2 II
Speed Grade
Units
-5
-4
9.71 10.68 ns
5.95 6.55
ns
4.24 4.66
ns
2.96 3.26
ns
2.39 2.63
ns
1.75 1.93
ns
1.30 1.43
ns
6.72 7.39
ns
2.88 3.17
ns
1.62 1.78
ns
0.48 0.52
ns
0.00 0.00
ns
–0.14 –0.15 ns
–0.23 –0.26 ns
–0.32 –0.36 ns
–0.26 –0.29 ns
–0.19 –0.21 ns
–0.18 –0.19 ns
–0.21 –0.23 ns
0.69 0.76
ns
–0.21 –0.23 ns
0.30 0.33
ns
1.19 1.31
ns
–0.01 –0.01 ns
–0.01 –0.01 ns
–0.32 –0.36 ns
–0.18 –0.20 ns
0.27 0.29
ns
–0.16 –0.17 ns
–0.17 –0.19 ns
– –0.45 ns
0.03 0.04
ns
–0.18 –0.20 ns
–0.16 –0.18 ns
–0.40 –0.44 ns
0.22 0.24
ns
–0.16 –0.18 ns
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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