XQ2V1000_1 Datasheet, PDF (10/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

R
X-Ref Target - Figure 4
CLOCK
QPro Virtex-II 1.5V Platform FPGAs
D1
Q1
CLK1
D2
Q2
CLK2
FDDR
DCM
180° 0°
DDR MUX
Q
D1
Q1
CLK1
D2
Q2
CLK2
FDDR
DDR MUX
Q
X-Ref Target - Figure 5
(50/50 duty cycle clock)
Figure 4: Double Data Rate Registers
DS031_26_100900
(O/T) 1
(O/T) CE
(O/T) CLK1
Shared ^SR
by all
registers REV
(O/T) CLK2
(O/T) 2
FF
LATCH
D1 ^Q1
Attribute INIT1
INIT0
SRHIGH
SRLOW
CE
CK1
SR REV
FF1
DDR MUX
FF2
(OQ or TQ)
FF
LATCH
D2 Q2
CE
CK2
SR REV
Attribute _INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
Figure 5: Register/Latch Configuration in an IOB Block
DS031_25_110300
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
10