XQ2V1000_1 Datasheet, PDF (1/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
DS122 (v2.0) December 21, 2007 ^{0 0}
Product Specification
Summary of QPro™ Virtex™-II Features
• Industry’s first military-grade platform FPGA solution
• Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
• 100% factory tested
• Guaranteed over the full military temperature range
(–55°C to +125°C) or industrial temperature range
(–40°C to +100°C)
• Ceramic and plastic wire-bond and flip-chip grid array
packages
• IP-immersion architecture
• High-performance clock management circuitry
♦ Up to 12 DCM (Digital Clock Manager) modules
- Precise clock de-skew
- Flexible frequency synthesis
- High-resolution phase shifting
♦ 16 global clock multiplexer buffers
• Active interconnect technology
♦ Fourth-generation segmented routing structure
♦ Predictable, fast routing delay, independent of fanout
♦ Densities from 1M to 6M system gates
• SelectIO™-Ultra Technology
♦ 300+ MHz internal clock speed (Advance Data)
♦ Up to 824 user I/Os
♦ 622+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
♦ 19 single-ended and six differential standards
♦ Programmable sink current (2 mA to 24 mA) per I/O
♦ 2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
♦ Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
♦ Up to 1 Mb of distributed SelectRAM resources
♦ PCI compliant (32/33 MHz) at 3.3V
• High-performance interfaces to external memory
♦ Differential signaling
♦ DRAM interfaces
- SDR/DDR SDRAM
- Network FCRAM
- Reduced Latency DRAM
♦ SRAM interfaces
- SDR/DDR SRAM
- QDR SRAM
♦ CAM interfaces
• Arithmetic functions
♦ 622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
♦ Bus LVDS I/O
♦ Lightning Data Transport (LDT) I/O with current
driver buffers
♦ Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
♦ Built-in DDR input and output registers
♦ Proprietary high-performance SelectLink
Technology
♦ Dedicated 18-bit x 18-bit multiplier blocks
- High-bandwidth data path
♦ Fast look-ahead carry logic chains
• Flexible logic resources
- Double Data Rate (DDR) link
- Web-based HDL generation methodology
• Up to 67,584 internal registers/latches with Clock Enable
• Up to 67,584 look-up tables (LUTs) or cascadable 16-
bit shift registers
• Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
♦ Integrated VHDL and Verilog design flows
• Wide multiplexers and wide-input function support
• Horizontal cascade chain and sum-of-products support
♦ Compilation of 10M system gates designs
♦ Internet Team Design (ITD) tool
• Internal 3-state busing
© 2003, 2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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