XQ2V1000_1 Datasheet, PDF (5/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM
elements all use the same interconnect scheme and the
same access to the global routing matrix. Timing models
are shared, greatly improving the predictability of the
performance of high-speed designs.
There are a total of 16 global clock lines with eight available
per quadrant. In addition, 24 vertical and horizontal long lines
per row or column as well as massive secondary and local
routing resources provide fast interconnect. Virtex-II buffered
interconnects are relatively unaffected by net fanout, and the
interconnect layout is designed to minimize crosstalk.
Horizontal and vertical routing resources for each row or
column include:
• 24 long lines
• 120 hex lines
• 40 double lines
• 16 direct connect lines (total in all four directions)
Boundary-Scan
Boundary-Scan instructions and associated data registers
support a standard methodology for accessing and
configuring Virtex-II devices that complies with IEEE
standards 1149.1 — 1993 and 1532. A system mode and a
test mode are implemented. In system mode, a Virtex-II
device performs its intended mission even while executing
non-test boundary-scan instructions. In test mode,
boundary-scan test instructions control the I/O pins for
testing purposes. The Virtex-II Test Access Port (TAP)
supports BYPASS, PRELOAD, SAMPLE, IDCODE, and
USERCODE non-test instructions. The EXTEST, INTEST,
and HIGHZ test instructions are also supported.
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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