XQ2V1000_1 Datasheet, PDF (37/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
X-Ref Target - Figure 45
S
CLK0
CLK1
OUT
Wait for Low
Switch
Local Clocking
In addition to global clocks, there are local clock resources
in the Virtex-II devices. There are more than 72 local clocks
in the Virtex-II family. These resources can be used for
many different applications, including but not limited to
memory interfaces. For example, even using only the left
and right I/O banks, Virtex-II FPGAs can support up to 50
local clocks for DDR SDRAM. These interfaces can operate
beyond 200 MHz on Virtex-II devices.
DS031_46_112900
Figure 45: Clock Multiplexer Waveform Diagram
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
37