XQ2V1000_1 Datasheet, PDF (35/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in Figure 39.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II devices.
Like the clock pads, eight global clock multiplexer buffers are
on the top edge of the device and eight are on the bottom.
X-Ref Target - Figure 39
8 clock pads
Virtex-II
Device
8 clock pads
DS031_42_101000
Figure 39: Virtex-II Clock Pads
Each global clock buffer can be driven by either the clock pad
to distribute a clock directly to the device, or the Digital Clock
Manager (DCM), discussed in "Digital Clock Manager (DCM),"
page 38. Each global clock buffer can also be driven by local
interconnects. The DCM has clock output(s) that can be
connected to global clock buffer inputs, as shown in Figure 40.
X-Ref Target - Figure 40
Clock
Pad
I
Clock
Pad
Clock
Buffer
0
Clock Distribution
CLKIN
DCM
CLKOUT
I
Clock
Buffer
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks).
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock
distribution detail of the device prior to pin-locking and
floorplanning (see [Ref 1]).
Figure 42 shows clock distribution in Virtex-II devices.
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to
multiplex between two independent clock inputs (BUFGMUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in Figure 41.
X-Ref Target - Figure 41
BUFG
I
O
DS031_61_101200
Figure 41: Virtex-II BUFG Function
The Virtex-II global clock buffer BUFG can also be
configured as a clock enable/disable circuit (Figure 43), as
well as a two-input clock multiplexer (Figure 44). A functional
description of these two options is provided below. Each of
them can be used in either of two modes, selected by
configuration: rising clock edge or falling clock edge.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX
primitives. The falling clock edge option uses the
BUFGCE_1 and BUFGMUX_1 primitives.
0
Clock Distribution
DS031_43_101000
Figure 40: Virtex-II Clock Distribution Configurations
DS122 (v2.0) December 21, 2007
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Product Specification
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