XQ2V1000_1 Datasheet, PDF (21/134 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Platform FPGAs

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QPro Virtex-II 1.5V Platform FPGAs
X-Ref Target - Figure 18
FFY
FF
LATCH
DY
D
Q
YQ
CE
Attribute
CK
INIT1
SR REV
INIT0
BY
SRHIGH
SRLOW
FFX
FF
LATCH
DX
D
Q
XQ
CE
Attribute
CE
INIT1
CLK
CK
SR REV
INIT0
SRHIGH
SRLOW
SR
Reset Type
BX
SYNC
ASYNC
DS031_22_110600
Figure 18: Register/Latch Configuration in a Slice
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:
• Single-port 16 x 8 bit RAM
• Single-port 32 x 4 bit RAM
• Single-port 64 x 2 bit RAM
• Single-port 128 x 1 bit RAM
• Dual-port 16 x 4 bit RAM
• Dual-port 32 x 2 bit RAM
• Dual-port 64 x 1 bit RAM
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies high-
speed designs. A synchronous read can be implemented
with a storage element in the same slice. The distributed
SelectRAM memory and the storage element share the
same clock input. A Write Enable (WE) input is active High,
and is driven by the SR input.
Table 13 shows the number of LUTs (two per slice)
occupied by each distributed SelectRAM configuration.
Table 13: Distributed SelectRAM Configurations
RAM
Number of LUTs
16 x 1S
1
16 x 1D
2
32 x 1S
2
32 x 1D
4
64 x 1S
4
64 x 1D
8
128 x 1S
8
Notes:
1. S = single-port configuration, and D = dual-port configuration.
For single-port configurations, distributed SelectRAM
memory has one address port for synchronous writes and
asynchronous reads.
For dual-port configurations, distributed SelectRAM
memory has one port for synchronous writes and
asynchronous reads and another port for asynchronous
reads. The function generator (LUT) has separated read
address inputs (A1, A2, A3, A4) and write address inputs
(WG1/WF1, WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function
generator (R/W port) is connected with shared read and
write addresses. The second function generator has the A
inputs (read) connected to the second read-only port
address and the W inputs (write) shared with the first
read/write port address.
Figure 19, Figure 20, page 22, and Figure 21, page 22
illustrate various example configurations.
X-Ref Target - Figure 19
RAM 16x1S
A[3:0] ⁴
4
RAM
A[4:1] D
WG[4:1]
WS DI
D ^(BY)
WE
WCLK
WSG
(SR) _WE
CK
DQ
Output
Registered
Output
(optional)
DS031_02_100900
Figure 19: Distributed SelectRAM (RAM16x1S)
DS122 (v2.0) December 21, 2007
www.xilinx.com
Product Specification
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