W83627DHG Datasheet, PDF (93/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
Bit 1: SYSFANIN output value, only if bit 0 is set to zero.
1: Pin113 (SYSFANIN) generates a logic-high signal.
0: Pin113 generates a logic-low signal. (Default)
Bit 0: SYSFANIN Input Control.
1: Pin113 (SYSFANIN) acts as a FAN tachometer input. (Default)
0: Pin113 acts as a FAN control signal, and the output value is set by bit 1.
8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0)
Register Location:
4Eh
Power on Default Value:
80h
Attribute:
Read/Write
Size:
8 bits
7 65432 1 0
BANKSEL0
BANKSEL1
BANKSEL2
Reserved
EN_CPUFANIN1_BP
EN_AUXFANIN1_BP
Reserved
HBACS
Bit 7: HBACS - High byte access.
1: Access Index 4Fh high-byte register. (Default)
0: Access Index 4Fh low-byte register.
Bit 6: Reserved. This bit should be set to zero.
Bit 5: BEEP output control for AUXFANIN1 if the monitored value exceeds the threshold value.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
Bit 4: BEEP output control for CPUFANIN1 if the monitored value exceeds the threshold value.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
Bit 3: Reserved. This bit should be set to zero.
Bit 2-0: Bank Select for Index Ports 0x50h~0x5Fh. The three-bit binary value corresponds to the bank
number. For example, “010” selects bank2.
8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0)
Register Location:
4Fh
Power on Default Value:
<15:0> = 5CA3h
Attribute:
Read Only
Size:
16 bits
Publication Release Date: Aug, 22, 2007
-81-
Version 1.4