W83627DHG Datasheet, PDF (32/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
5.11.4 GPIO-3 Interface
SYMBOL PIN
I/O
RSTOUT0# 94 OD₁₂
RSTOUT1# 93
O₁₂
GP30
PWROK2
I/OD_12t
92
OD₁₂
GP31
I/OD_12t
91
VSBGATE#
O₁₂
GP32
RSTOUT2#
SCL
GP33
RSTOUT3#
SDA
GP34
RSTOUT4#
GP35
ATXPGD
I/OD_12t
90
O₁₂
IN_ts
I/OD_12t
89
O₁₂
I/OD_12ts
88
I/OD_12t
O₁₂
I/OD_12t
87
IN_t
GP36
FTPRST#
GP37
SUSC#
I/OD_12t
69
IN_t
I/OD_12t
64
IN_t
DESCRIPTION
PCI Reset Buffer 0.
PCI Reset Buffer 1.
General-purpose I/O port 3 bit 0.
This pin generates the PWROK2 signal while 3VCC comes in.
(This pin function is both for UBE and UBF version only)
General-purpose I/O port 3 bit 1.
Switch 3VSB power to memory when in S3 state. The default is
disabled while the particular ACPI functions are enabled. The
control bit is at Logical Device A, CR[E4h] bit 4.(This pin function
is both for UBE and UBF version only)
General-purpose I/O port 3 bit 2.
PCI Reset Buffer 2. (Default)
Serial Bus clock.
General-purpose I/O port 3 bit 3.
PCI Reset Buffer 3. (Default)
Serial bus bi-directional Data.
General-purpose I/O port 3 bit 4.
PCI Reset Buffer 4. (Default)
General-purpose I/O port 3 bit 5.
ATX power good input signal. It is connected to the PWROK
signal from the power supply for PWROK/PWROK2 generation.
The default is enabled.(This pin function is both for UBE and UBF
version only)
General-purpose I/O port 3 bit 6.
Connect to the reset button. This pin has internal de-bounce
circuit whose de-bounce time is at least 32 mS. (This pin function
is both for UBE and UBF version only)
General-purpose I/O port 3 bit 7.
SLP_S5# input. (This pin function is both for UBE and UBF
version only)
5.11.5 GPIO-4 Interface
See 5.4 Serial Port & Infrared Port Interface
Publication Release Date: Aug, 22, 2007
-20-
Version 1.4