W83627DHG Datasheet, PDF (203/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
20.4 Logical Device 2 (UART A)
CR 30h. (Default 01h)
BIT READ / WRITE
DESCRIPTION
7~1 Reserved.
0
R/W
0: Logical device is inactive.
1: Activate the logical device.
CR 60h, 61h. (Default 03h, F8h)
BIT READ / WRITE
DESCRIPTION
7~0
R/W
These two registers select Serial Port 1 I/O base address <100h: FF8h> on
8 bytes boundary.
CR 70h. (Default 04h)
BIT READ / WRITE
DESCRIPTION
7~4 Reserved.
3~0
R/W
These bits select IRQ resource for Serial Port 1.
CR F0h. (Default 00h)
BIT READ / WRITE
7~2 Reserved.
DESCRIPTION
00: UART A clock source is 1.8462 MHz (24 MHz / 13).
01: UART A clock source is 2 MHz (24 MHz / 12).
1~0
R/W
00: UART A clock source is 24 MHz (24 MHz / 1).
00: UART A clock source is 14.769 MHz (24 MHz / 1.625).
20.5 Logical Device 3 (UART B)
CR 30h. (Default 01h)
BIT READ / WRITE
DESCRIPTION
7~1 Reserved.
0
R/W
0: Logical device is inactive.
1: Activate the logical device.
CR 60h, 61h. (Default 02h, F8h)
BIT READ / WRITE
DESCRIPTION
7~0
R/W
These two registers select Serial Port 2 I/O base address <100h: FF8h> on
eight-byte boundary.
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Publication Release Date: Aug, 22, 2007
Version 1.4