W83627DHG Datasheet, PDF (26/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
5.5 KBC Interface
SYMBOL
PIN
I/O
GA20M
59
O₁₂
KBRST
60
O₁₂
KCLK
GP27
62
I/OD_16ts
I/OD_16t
KDAT
GP26
63
I/OD_16ts
I/OD_16t
MCLK
GP25
65
I/OD_16ts
I/OD_16t
MDAT
GP24
66
I/OD_16ts
I/OD_16t
DESCRIPTION
Gate A20 output. This pin is high after system reset. (KBC P21)
Keyboard reset. This pin is high after system reset. (KBC P20)
Keyboard Clock.
General-purpose I/O port 2 bit 7.
Keyboard Data.
General-purpose I/O port 2 bit 6.
PS2 Mouse Clock.
General-purpose I/O port 2 bit 5.
PS2 Mouse Data.
General-purpose I/O port 2 bit 4.
5.6 Serial Peripheral Interface
The SPI employs a master-slave model and typically has three signal lines: serial data input line (SI),
serial data output line (SO), and serial clock line (SCK). Different slaves are addressed on the bus by
chip select signals from the master. The data bits are first shifted in/out the most significant bit (MSB).
The data are often shifted simultaneously out from the output pin and into the input pin. Among the
parameters, only the communication lines and the clock edge are defined by the SPI. The others differ
from device to device.
SPI Operation
To initiate the data transfer between the W83627DHG and a slave device, SCE# must go low. This
synchronizes the slave device with the W83627DHG. Data can now be transferred between the
W83627DHG and the slave device in one of two modes: the data is sampled either on the rising or the
falling edge of the clock.
In a slave device, a logic low is received on the SCE# line and the clock input is at the SCK pin, which
synchronizes the slave with the W83627DHG. Data is then received serially at the SI pin. During a write
cycle, data is shifted out to the SO pin on clocks from the W83627DHG.
Publication Release Date: Aug, 22, 2007
-14-
Version 1.4