W83627DHG Datasheet, PDF (146/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
765 43
00 0
21
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG#
DSKCHG (Bit 7):
This bit indicates the status of the DSKCHG# input.
Bit 6-4: These bits are always a logic 0 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO register, bit 3.
NOPREC (Bit 2):
This bit indicates the value of the NOPREC bit in the CC REGISTER.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
10.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as follows:
7 6 5 ^{4 3 21} 0
xxxx xx
X: Reserved
DRATE0
DRATE1
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
-134-
Publication Release Date: Aug, 22, 2007
Version 1.4